
Summary of hardware requirements for cycle accuracy:
----------------------------------------------------
ADR7 -> C Flag  - wait for implementaion of other flag logic!
W -> A, X, SP - OR gates on Registers card
A&X -> R -shadow register on ALU card
DPH+1 -> B; shadow register on ALU card; Use DPH+1 signal to trigger YWR - need a 74'541 connecting the Y Bus to the Data Bus to avoid the usual delay through the ALU. YWR disables the R bus going to the Data bus during the write.
ARR Binary mode flag evaluation
ARR Decimal mode flag evaluation

Microcode
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SAX	$87	zpg	2	3		SAX (adr) = store A&X into (adr)	
	DPL := *PC; PC += 1						
	*zDP := A&X			// A&X-> R	
	IR := *PC; PC += 1; END			

SAX	$97	zpg,y	2	4			
	B := *PC; PC += 1						
	DPL := B + X;						
	*zDP := A&X			// A&X-> R	
	IR := *PC; PC += 1; END
						
SAX	$83	(ind,X)	2	6			
	B := *PC; PC += 1						
	DPL := B + X;						
	T := *zDP; DPL += 1						
	DPH := *zDP						
	*DPt := A&X			// A&X-> R	
	IR := *PC; PC += 1; END						
							
SAX	$8F	Abs	3	4			
	DPL := *PC; PC += 1						
	DPH := *PC; PC += 1						
	*DP := A&X			// A&X-> R	
	IR := *PC; PC += 1; END						
				
SHX	$9E	abs,y	3	5		Store X AND highbyte(addr)+1 to addr	
	B := *PC; PC += 1						
	DPL := B + Y; DPH.db := *PC; PC += 1						
	DPH := DPH + 0; USE(IC)						
	*DP := X AND DPH+1; YWR		// DPH+1 -> B; YWR
	IR := *PC; PC += 1; END						
							
SHY	$9C	abs,x	3	5		Store Y AND highbyte(addr)+1 to addr	
	B := *PC; PC += 1						
	DPL := B + X; DPH.db := *PC; PC += 1						
	DPH := DPH + 0; USE(IC)						
	*DP := Y AND DPH+1; YWR		// DPH+1 -> B; Y Bus -> DB
	IR := *PC; PC += 1; END						
							
LAS	$BB 	abs,y	3	4*	NZ	SP & M -> A, X, SP	
	B := *PC; PC += 1						
	DPL := B + Y; DPH.db := *PC; PC += 1; SKIP.CC						
	DPH := DPH + 1						
	B := *DP						
	AXS := SP AND B; SETF(NZ); IR := *PC; PC += 1; END	// W -> A, X, SP
							
AXS	$CB	imm	2	2	NZC	AXS #(imm) = A&X minus #(imm) into X ; named SBX in VICE	
	B := *PC; PC += 1						
	X := A&X SBC1 B; SETF(NZC); IR := *PC; PC += 1; END	// A&X -> R, SBC1 = SBC w/ C = 1. Always binary mode

TAS	$9B	abs,y	3	5		Store A&X into S, store A&X&H+1 into (adr)
	B := *PC; PC += 1			
	DPL := B + Y; DPH.db := *PC; PC += 1	
	DPH := DPH + 0; USE(IC)						
	*DP := A&X AND DPH+1; YWR		// A&X -> R, DPH+1 -> B, Y Bus -> DB
	SP := A&X; IR := *PC; PC += 1; END	// A&X -> R	
							
AHX	$9F	abs,Y	3	5		AHX (addr) = store A&X&H+1 into (adr)	
	B := *PC; PC += 1						
	DPL := B + Y; DPH.db := *PC; PC += 1						
	DPH := DPH + 0; USE(IC)						
	*DP := A&X AND DPH+1			// A&X -> R, DPH+1 -> B; Y Bus -> DB	
	IR := *PC; PC += 1; END						
							
AHX	$93	(ind),Y	2	6			
	DPL := *PC; PC += 1						
	B := *zDP; DPL += 1						
	T := B + Y; DPH.db := *zDP						
	DPH := DPH + 0; USE(IC)			
	*DPt := A&X AND DPH+1; YWR		// A&X -> R, DPH+1 -> B, Y Bus -> DB
	IR := *PC; PC += 1; END						
							
ANC	$0B	Imm	2	2	NZC	A AND imm -> A	
	$2B	Imm	2	2	NZC		
	B := *PC; PC += 1						
	A := A AND B; SETF(NZC=b7); IR := *PC; PC += 1; END // ADR.7 -> C Flag
		 
ARR	$6B	imm	2	2	NZCV	AND byte with accumulator, then rotate one bit right in accu-mulator	
	B := *PC; PC += 1						
	A := A AND B; ROR A; SETF(NZ); IR := *PC; PC += 1; END		// NZ are set as usual, but what are CV??
							
							tmp1 := A & #imm
							tmp2 := "ROR" tmp1 //C_Flag goes into tmp2.7
							
							//Result = tmp2
							
							N_Flag := tmp2.7 // = ROR input carry
							Z_Flag := set if tmp2=$00
							C_Flag := tmp2.6
							V_Flag := tmp2.6 XOR tmp2.5

As an aside, I wasn't able to follow the logic for ARR in binary mode. I see the N and Z flags are computed as usual from the result after the ROR but I don't fully understand how to evaluate the C and V flags. You had suggested:

C_Flag := tmp2.6
V_Flag := tmp2.6 XOR tmp2.5

but I don't quite follow the logic here. It seems I would have to design special circuitry to set the C and V flags according to this. Is that right?

------

To clarify things with ARR: 
A & #imm is done by the LUs, so tmp1 would be on Y7..0 and on ADR7..0.
V_Flag := ADR7 XOR ADR6.
N_Flag := previous C_Flag //because of the "ROR".

In ARR binary mode, C_Flag := ADR7 //like with ANC !
In ARR decimal mode, C_Flag only is set if ADR7..0 >= $5X.

Z_Flag evaluation won't be fun:
ARR checks tmp2, NMOS BCD checks ADR7..0, "the rest" checks W7..0.

Note, that NVZ flag evaluation in binary and decimal ARR seems to be exactly the same.
Just C flag is evaluated different in binary and decimal ARR.

BTW: I still have no clue about what goes on in a real NMOS 6502\6510 to make such things as ARR happen...
I don't know. I don't _want_ to know. :mrgreen:




